Mask Wafer Co-Optimization Throws Lithography a Curve with Innovative Research Approach

Mask Wafer Co-Optimization: Revolutionizing Semiconductor Chip Technology

The Challenge of Creating Smaller, More Efficient Electronic Components

Advancing semiconductor chip technology is at the forefront of innovation in the electronics industry, driving the need for smaller and more efficient electronic components. One of the critical challenges in achieving this advancement lies in the field of lithography, the process essential for creating intricate patterns on semiconductor materials, known as wafers, to produce chips.

Lithography involves using a template called a photomask or mask, which is crucial for creating patterns on semiconductor wafers. The industry constantly seeks methods to enhance resolution and manufacturability for both masks and wafers, aiming to produce faster chips with a higher yield of properly functioning chips. Computational lithography techniques such as optical proximity correction (OPC) have been pivotal in improving resolution and pattern fidelity by modifying individual mask patterns to enhance both mask and wafer printing.

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The Emergence of Inverse Lithography Technology (ILT)

Inverse lithography technology (ILT) is a mathematically rigorous inverse approach that determines mask shapes capable of producing the desired on-wafer results. This technology has shown promise in addressing the challenges of lithography for advanced chips. Studies have demonstrated that curvilinear ILT mask shapes, in particular, yield the best wafer results. However, the practical application of this computational technique was limited due to long runtimes, restricting its usage to critical “hotspots” on chips.

In 2019, a novel system was proposed, featuring a unique GPU-accelerated approach that enabled the computation of an entire full-chip ILT solution at once, making full-chip ILT a practical reality in production. This approach relied on multi-beam mask writing, a significant development in mask writing that is pixel-based and shape-agnostic in terms of write-time.

Introducing Mask Wafer Co-Optimization (MWCO)

Addressing the challenge of extending the benefits of full-chip, curvilinear ILT to variable shaped beam (VSB) mask writers, D2S, Inc. introduced a groundbreaking method called mask wafer co-optimization (MWCO). This method leverages three key insights:

1. **Mask Writer and Wafer Scanner as Low-Pass Filters**: Recognizing that both the mask writer and wafer scanner act as low-pass filters, MWCO utilizes overlapping shots guided by mask/wafer simulation to create curvilinear shapes with fewer shots.

2. **Targeting the Wafer Pattern**: By focusing on the wafer pattern rather than the mask pattern, MWCO simplifies shot creation to print the correct wafer pattern. This approach optimizes wafer print quality iteratively while manipulating VSB shot edges to produce rectilinear target mask shapes suitable for VSB writers.

3. **Double Simulation for Optimization**: Through a double simulation process, MWCO ensures that wafer print quality is optimized, leading to a 3x reduction in wafer variation and a 2x enhancement in the wafer process window compared to traditional methods like Micron OPC.

Through collaboration with Micron Technology, D2S demonstrated that MWCO significantly improves the precision and reliability of the lithography process. This advancement allows semiconductor manufacturers to produce smaller chips with enhanced performance and lower power consumption, even without access to a multi-beam mask writer.

Implications for the Semiconductor Industry

The introduction of mask wafer co-optimization represents a significant milestone in semiconductor chip technology. By combining the power of variable shaped beam mask writers with curvilinear full-chip inverse lithography technology, MWCO enables the production of advanced chips with unprecedented precision and efficiency.

With MWCO, semiconductor manufacturers can achieve high-volume production requirements with a write time for a full curvilinear ILT mask of less than 12 hours. This breakthrough not only leads to the creation of smaller and more efficient electronic components but also paves the way for further innovations in semiconductor chip technology.

Mask wafer co-optimization marks a paradigm shift in lithography techniques, offering a path towards the next generation of semiconductor chip technology. By optimizing the interaction between mask writers and wafer scanners, MWCO opens up new possibilities for the development of faster, more reliable, and energy-efficient electronic devices.

Links to additional Resources:

1. Nature.com 2. ScienceDirect.com 3. ASML.com. 

Related Wikipedia Articles

Topics: Semiconductor chip technology, Lithography, Mask wafer co-optimization

Semiconductor device fabrication
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM) that are present in everyday electronic devices. It is a multiple-step photolithographic and physio-chemical process (with steps such as thermal oxidation,...
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Lithography
Lithography (from Ancient Greek λίθος, lithos 'stone', and γράφω, graphō 'to write') is a planographic method of printing originally based on the immiscibility of oil and water. The printing is from a stone (lithographic limestone) or a metal plate with a smooth surface. It was invented in 1796 by the...
Read more: Lithography

Semiconductor device fabrication
Semiconductor device fabrication is the process used to manufacture semiconductor devices, typically integrated circuits (ICs) such as computer processors, microcontrollers, and memory chips (such as NAND flash and DRAM) that are present in everyday electronic devices. It is a multiple-step photolithographic and physio-chemical process (with steps such as thermal oxidation,...
Read more: Semiconductor device fabrication